Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-21
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4.3.8 System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 255,
of the exception handlers that have
configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 4-12 on page 4-11 for
their attributes.
To access to the system exception priority level using CMSIS, use the following CMSIS
functions:
•
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
•
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
The input parameter IRQn is the IRQ number, see Table 2-16 on page 2-22 for more
information.
System Handler Priority Register 1
The bit assignments are:
[2] - Reserved.
[1] USERSETMPEND Enables unprivileged software access to the STIR, see Software Trigger Interrupt
Register on page 4-8:
0 = disable
1 = enable.
[0] NONBASETHRDENA Indicates how the processor enters Thread mode:
0 = processor can enter Thread mode only when no exception is active.
1 = processor can enter Thread mode from any level under the control of an
EXC_RETURN value, see Exception return on page 2-28.
Table 4-20 CCR bit assignments (continued)
Bits Name Function
Table 4-21 SHPR1 register bit assignments
Bits Name Function
[31:24] PRI_7 Reserved.
[23:16] PRI_6 Priority of system handler 6, UsageFault
[15:8] PRI_5 Priority of system handler 5, BusFault
[7:0] PRI_4 Priority of system handler 4, MemManage
31 24 23 0
Reserved PRI_6 PRI_5 PRI_4
16 15 8 7
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