ARM Cortex-M4 - Nested Vectored Interrupt Controller

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-3
ID121610 Non-Confidential
4.2 Nested Vectored Interrupt Controller
This section describes the NVIC and the registers it uses. The NVIC supports:
• An implementation-defined number of interrupts, in the range 1-240 interrupts.
• A programmable priority level of 0-255 for each interrupt. A higher level corresponds to
a lower priority, so level 0 is the highest interrupt priority.
• Level and pulse detection of interrupt signals.
• Dynamic reprioritization of interrupts.
• Grouping of priority values into group priority and subpriority fields.
• Interrupt tail-chaining.
• An external Non Maskable Interrupt (NMI)
• Optional WIC, providing ultra-low power sleep mode support.
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling. The
hardware implementation of the NVIC registers is:
Table 4-2 NVIC register summary
Address Name Type
Required
privilege
Reset value Description
0xE000E100 -
0xE000E11C
NVIC_ISER0-
NVIC_ISER7
RW Privileged 0x00000000 Interrupt Set-enable Registers on page 4-4
0XE000E180 -
0xE000E19C
NVIC_ICER0-
NVIC_ICER7
RW Privileged 0x00000000 Interrupt Clear-enable Registers on page 4-5
0XE000E200 -
0xE000E21C
NVIC_ISPR0-
NVIC_ISPR7
RW Privileged 0x00000000 Interrupt Set-pending Registers on page 4-5
0XE000E280 -
0xE000E29C
NVIC_ICPR0-
NVIC_ICPR7
RW Privileged 0x00000000 Interrupt Clear-pending Registers on page 4-6
0xE000E300 -
0xE000E31C
NVIC_IABR0-
NVIC_IABR7
RW Privileged 0x00000000 Interrupt Active Bit Registers on page 4-7
0xE000E400 -
0xE000E4EF
NVIC_IPR0-
NVIC_IPR59
RW Privileged 0x00000000 Interrupt Priority Registers on page 4-7
0xE000EF00 STIR WO
Configurable
a
0x00000000 Software Trigger Interrupt Register on page 4-8
a. See the register description for more information.