Introduction
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 1-3
ID121610 Non-Confidential
Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the
hardware stacking of registers, and the ability to suspend load-multiple and store-multiple
operations. Interrupt handlers do not require wrapping in assembler code, removing any code
overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when
switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that includes an
optional deep sleep function. This enables the entire device to be rapidly powered down while
still retaining program state.
1.1.1 System-level interface
The Cortex-M4 processor provides multiple interfaces using AMBA
®
technology to provide
high speed, low latency memory accesses. It supports unaligned data accesses and implements
atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe
Boolean data handling.
The Cortex-M4 processor has an optional Memory Protection Unit (MPU) that permits control
of individual regions in memory, enabling applications to utilize multiple privilege levels,
separating and protecting code, data and stack on a task-by-task basis. Such requirements are
becoming critical in many embedded applications such as automotive.
1.1.2 Optional integrated configurable debug
The Cortex-M4 processor can implement a complete hardware debug solution. This provides
high system visibility of the processor and memory through either a traditional JTAG port or a
2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package
devices.
For system trace the processor integrates an Instrumentation Trace Macrocell (ITM) alongside
data watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system
events these generate, a Serial Wire Viewer (SWV) can export a stream of software-generated
messages, data trace, and profiling information through a single pin.
The optional Embedded Trace Macrocell
™
(ETM) delivers unrivalled instruction trace capture
in an area far smaller than traditional trace units, enabling many low cost MCUs to implement
full instruction trace for the first time.
The optional Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint
comparators that debuggers can use. The comparators in the FPB also provide remap functions
of up to eight words in the program code in the CODE memory region. This enables applications
stored on a non-erasable, ROM-based microcontroller to be patched if a small programmable
memory, for example flash, is available in the device. During initialization, the application in
ROM detects, from the programmable memory, whether a patch is required. If a patch is
required, the application programs the FPB to remap a number of addresses. When those
addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration, which means the program in the non-modifiable ROM can be patched.
1.1.3 Cortex-M4 processor features and benefits summary
• tight integration of system peripherals reduces area and development costs
• Thumb instruction set combines high code density with 32-bit performance
• optional IEEE754-compliant single-precision FPU
• code-patch ability for ROM system updates
• power control optimization of system components
• integrated sleep modes for low power consumption
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