ARM Cortex-M4 - Chapter 3 The Cortex-M4 Instruction Set; Instruction Set Summary

The Cortex-M4 Instruction Set
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3.1 Instruction set summary
The processor implements a version of the Thumb instruction set. Table 3-1 lists the supported
instructions.
Note
In Table 3-1:
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
•
Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
For more information on the instructions and operands, see the instruction descriptions.
Table 3-1 Cortex-M4 instructions
Mnemonic Operands Brief description Flags Page
ADC, ADCS {Rd,} Rn, Op2 Add with Carry N,Z,C,V page 3-41
ADD, ADDS {Rd,} Rn, Op2 Add N,Z,C,V page 3-41
ADD, ADDW {Rd,} Rn, #imm12 Add - page 3-41
ADR Rd, label Load PC-relative Address - page 3-23
AND, ANDS {Rd,} Rn, Op2 Logical AND N,Z,C page 3-44
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right N,Z,C page 3-46
B label Branch - page 3-119
BFC Rd, #lsb, #width Bit Field Clear - page 3-115
BFI Rd, Rn, #lsb, #width Bit Field Insert - page 3-115
BIC, BICS {Rd,} Rn, Op2 Bit Clear N,Z,C page 3-44
BKPT #imm Breakpoint - page 3-158
BL label Branch with Link - page 3-119
BLX Rm Branch indirect with Link - page 3-119
BX Rm Branch indirect - page 3-119
CBNZ Rn, label Compare and Branch if Non Zero - page 3-121
CBZ Rn, label Compare and Branch if Zero - page 3-121
CLREX - Clear Exclusive - page 3-38
CLZ Rd, Rm Count Leading Zeros - page 3-48
CMN Rn, Op2 Compare Negative N,Z,C,V page 3-49
CMP Rn, Op2 Compare N,Z,C,V page 3-49
CPSID i Change Processor State, Disable Interrupts - page 3-159
CPSIE i Change Processor State, Enable Interrupts - page 3-159