ARM Cortex-M4 - LDR and STR, Unprivileged

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-29
ID121610 Non-Confidential
3.4.4 LDR and STR, unprivileged
Load and Store with unprivileged access.
Syntax
op{type}T{cond} Rt, [Rn {, #offset}] ; immediate offset
where:
op Is one of:
LDR Load Register.
STR Store Register.
type Is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits ( LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits ( LDR only).
- omit, for word.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rt Specifies the register to load or store.
Rn Specifies the register on which the memory address is based.
offset Specifies an offset from Rn and can be 0 to 255. If offset is omitted, the address
is the value in
Rn .
Operation
These load and store instructions perform the same function as the memory access instructions
with immediate offset, see LDR and STR, immediate offset on page 3-24. The difference is that
these instructions have only unprivileged access even when used in privileged software.
When used in unprivileged software, these instructions behave in exactly the same way as
normal memory access instructions with immediate offset.
Restrictions
In these instructions:
•
Rn must not be PC
•
Rt must not be SP and must not be PC.
Condition flags
These instructions do not change the flags.
Examples
STRBTEQ R4, [R7] ; Conditionally store least significant byte in
; R4 to an address in R7, with unprivileged access
LDRHT R2, [R2, #8] ; Load halfword value from an address equal to
; sum of R2 and 8 into R2, with unprivileged access.