ARM Cortex-M4 - MUL, MLA, and MLS

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-75
ID121610 Non-Confidential
3.6.1 MUL, MLA, and MLS
Multiply, Multiply with Accumulate, and Multiply with Subtract, using 32-bit operands, and
producing a 32-bit result.
Syntax
MUL{S}{cond} {Rd,} Rn, Rm ; Multiply
MLA{cond} Rd, Rn, Rm, Ra ; Multiply with accumulate
MLS{cond} Rd, Rn, Rm, Ra ; Multiply with subtract
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
S Is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see Conditional execution on page 3-18.
Rd Specifies the destination register. If Rd is omitted, the destination register is Rn .
Rn, Rm Are registers holding the values to be multiplied.
Ra Is a register holding the value to be added or subtracted from.
Operation
The
MUL instruction multiplies the values from Rn and Rm , and places the least significant 32 bits
of the result in
Rd .
The
MLA instruction multiplies the values from Rn and Rm , adds the value from Ra , and places the
least significant 32 bits of the result in
Rd .
The
MLS instruction multiplies the values from Rn and Rm , subtracts the product from the value
from
Ra , and places the least significant 32 bits of the result in Rd .
The results of these instructions do not depend on whether the operands are signed or unsigned.