ARM Cortex-M4 - Usagefault Status Register; UFSR Bit Assignments

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-28
ID121610 Non-Confidential
UsageFault Status Register
The UFSR indicates the cause of a UsageFault. The bit assignments are:
NOCP
INVPC
INVSTATE
UNDEFINSTR
DIVBYZERO
UNALIGNED
15 10987 43210
Reserved Reserved
Table 4-27 UFSR bit assignments
Bits Name Function
[15:10] - Reserved.
[9] DIVBYZERO Divide by zero UsageFault:
0 = no divide by zero fault, or divide by zero trapping not enabled
1 = the processor has executed an
SDIV or UDIV instruction with a divisor of 0.
When the processor sets this bit to 1, the PC value stacked for the exception return points to the instruction
that performed the divide by zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see Configuration and
Control Register on page 4-19.
[8] UNALIGNED Unaligned access UsageFault:
0 = no unaligned access fault, or unaligned access trapping not enabled
1 = the processor has made an unaligned memory access.
Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see
Configuration and Control Register on page 4-19.
Unaligned
LDM , STM , LDRD , and STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
[7:4] - Reserved.
[3] NOCP No coprocessor UsageFault. The processor does not support coprocessor instructions:
0 = no UsageFault caused by attempting to access a coprocessor
1 = the processor has attempted to access a coprocessor.