ARM Cortex-M4 - LDREX and STREX

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-36
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3.4.8 LDREX and STREX
Load and Store Register Exclusive.
Syntax
LDREX{cond} Rt, [Rn {, #offset}]
STREX{cond} Rd, Rt, [Rn {, #offset}]
LDREXB{cond} Rt, [Rn]
STREXB{cond} Rd, Rt, [Rn]
LDREXH{cond} Rt, [Rn]
STREXH{cond} Rd, Rt, [Rn]
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register for the returned status.
Rt Specifies the register to load or store.
Rn Specifies the register on which the memory address is based.
offset Is an optional offset applied to the value in Rn . If offset is omitted, the address is
the value in
Rn .
Operation
LDREX , LDREXB , and LDREXH load a word, byte, and halfword respectively from a memory address.
STREX , STREXB , and STREXH attempt to store a word, byte, and halfword respectively to a memory
address. The address used in any Store-Exclusive instruction must be the same as the address in
the most recently executed Load-exclusive instruction. The value stored by the Store-Exclusive
instruction must also have the same data size as the value loaded by the preceding
Load-exclusive instruction. This means software must always use a Load-exclusive instruction
and a matching Store-Exclusive instruction to perform a synchronization operation, see
Synchronization primitives on page 2-18.
If an Store-Exclusive instruction performs the store, it writes 0 to its destination register. If it
does not perform the store, it writes 1 to its destination register. If the Store-Exclusive
instruction writes 0 to the destination register, it is guaranteed that no other process in the system
has accessed the memory location between the Load-exclusive and Store-Exclusive
instructions.
For reasons of performance, keep the number of instructions between corresponding
Load-Exclusive and Store-Exclusive instruction to a minimum.
Note
The result of executing a Store-Exclusive instruction to an address that is different from that
used in the preceding Load-Exclusive instruction is unpredictable.