ARM Cortex-M4 - Exception Handlers; Vector Table

The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-23
ID121610 Non-Confidential
For an asynchronous exception, other than reset, the processor can execute another instruction
between when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-16 on page 2-22 shows as having
configurable priority, see:
• System Handler Control and State Register on page 4-23
• Interrupt Clear-enable Registers on page 4-5.
For more information about HardFaults, MemManage faults, BusFaults, and UsageFaults, see
Fault handling on page 2-29.
2.3.3 Exception handlers
The processor handles exceptions using:
Interrupt Service Routines (ISRs)
The IRQ interrupts are the exceptions handled by ISRs.
Fault handlers HardFault, MemManage fault, UsageFault, and BusFault are fault
exceptions handled by the fault handlers.
System handlers NMI, PendSV, SVCall SysTick, and the fault exceptions are all system
exceptions that are handled by system handlers.
2.3.4 Vector table
The vector table contains the reset value of the stack pointer, and the start addresses, also called
exception vectors, for all exception handlers. Figure 2-2 on page 2-24 shows the order of the
exception vectors in the vector table. The least-significant bit of each vector must be 1,
indicating that the exception handler is Thumb code, see Thumb state on page 2-7.
11 -5 SVCall
Configurable
c
0x0000002C Synchronous
12-13 - Reserved - - -
14 -2 PendSV
Configurable
c
0x00000038 Asynchronous
15 -1 SysTick
Configurable
c
0x0000003C Asynchronous
16 0 Interrupt (IRQ)
Configurable
d
0x00000040
e
Asynchronous
a. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than
interrupts. The IPSR returns the Exception number, see Interrupt Program Status Register on page 2-6.
b. See Vector table for more information.
c. See System Handler Priority Registers on page 4-21.
d. See Interrupt Priority Registers on page 4-7.
e. Increasing in steps of 4.
Table 2-16 Properties of the different exception types (continued)
Exception
number
a
IRQ
number
a
Exception type Priority
Vector address
or offset
b
Activation