ARM Cortex-M4 - Vstr; Floating-Point Store

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-155
ID121610 Non-Confidential
3.11.28 VSTR
Floating-point Store.
Syntax
VSTR{cond}{.32} Sd, [Rn{, #imm}]
VSTR{cond}{.64} Dd, [Rn{, #imm}]
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
32, 64 Are the optional data size specifiers.
Sd Specifies the source register for a singleword store.
Dd Specifies the source register for a doubleword store.
Rn Specifies the base register. The SP can be used.
imm Is the + or - immediate offset used to form the address. Values are multiples of 4
in the range 0-1020.
imm can be omitted, meaning an offset of +0 .
Operation
This instruction:
• Stores a single extension register to memory, using an address from an ARM core register,
with an optional offset, defined in
imm .
Restrictions
The restrictions are:
• The use of PC for
Rn is deprecated.
Condition flags
These instructions do not change the flags.