ARM Cortex-M4 - LDR, PC-Relative

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-30
ID121610 Non-Confidential
3.4.5 LDR, PC-relative
Load register from memory.
Syntax
LDR{type}{cond} Rt, label
LDRD{cond} Rt, Rt2, label ; Load two words
where:
type Is one of:
B unsigned byte, zero extend to 32 bits.
SB signed byte, sign extend to 32 bits.
H unsigned halfword, zero extend to 32 bits.
SH signed halfword, sign extend to 32 bits.
- omit, for word.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rt Specifies the register to load or store.
Rt2 Specifies the second register to load or store.
label Is a PC-relative expression. See PC-relative expressions on page 3-17.
Operation
LDR loads a register with a value from a PC-relative memory address. The memory address is
specified by a label or by an offset from the PC.
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and
halfwords can either be signed or unsigned. See Address alignment on page 3-17.
label must be within a limited range of the current instruction. Table 3-7 shows the possible
offsets between
label and the PC.
Note
You might have to use the .W suffix to get the maximum offset range. See Instruction width
selection on page 3-21.
Restrictions
In these instructions:
•
Rt can be SP or PC only for word loads
•
Rt2 must not be SP and must not be PC
•
Rt must be different from Rt2.
Table 3-7 Offset ranges
Instruction type Offset range
Word, halfword, signed halfword, byte, signed byte −4095 to 4095
Two words −1020 to 1020