ARM Cortex-M4 - QADD and QSUB

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-98
ID121610 Non-Confidential
3.7.3 QADD and QSUB
Saturating Add and Saturating Subtract, signed.
Syntax
op{cond} {Rd}, Rn, Rm
op{cond} {Rd}, Rn, Rm
where:
op Is one of:
QADD Saturating 32-bit add.
QADD8 Saturating four 8-bit integer additions.
QADD16 Saturating two 16-bit integer additions.
QSUB Saturating 32-bit subtraction.
QSUB8 Saturating four 8-bit integer subtraction.
QSUB16 Saturating two 16-bit integer subtraction.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register.
Rn, Rm Are registers holding the first and second operands.
Operation
These instructions add or subtract two, four or eight values from the first and second operands
and then writes a signed saturated value in the destination register.
The
QADD and QSUB instructions apply the specified add or subtract, and then saturate the result to
the signed range −2
n–1
≤ x ≤ 2
n–1
−1, where x is given by the number of bits applied in the
instruction, 32, 16 or 8.
If the returned result is different from the value to be saturated, it is called saturation. If
saturation occurs, the
QADD and QSUB instructions set the Q flag to 1 in the APSR. Otherwise, it
leaves the Q flag unchanged. The 8-bit and 16-bit
QADD and QSUB instructions always leave the Q
flag unchanged.
To clear the Q flag to 0, you must use the
MSR instruction, see MSR on page 3-164.
To read the state of the Q flag, use the
MRS instruction, see MRS on page 3-163.
Restrictions
Do not use SP and do not use PC
.
Condition flags
These instructions do not affect the condition code flags.
If saturation occurs, these instructions set the Q flag to 1.