ARM Cortex-M4 - Base Priority Mask Register; CONTROL Register

The Cortex-M4 Processor
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Base Priority Mask Register
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI
is set to a nonzero value, it prevents the activation of all exceptions with the same or lower
priority level as the BASEPRI value. See the register summary in Table 2-2 on page 2-3 for its
attributes. The bit assignments are:
CONTROL register
The CONTROL register controls the stack used and the privilege level for software execution
when the processor is in Thread mode and, if implemented, indicates whether the FPU state is
active. See the register summary in Table 2-2 on page 2-3 for its attributes. The bit assignments
are:
Handler mode always uses the MSP, so the processor ignores explicit writes to the active stack
pointer bit of the CONTROL register when in Handler mode. The exception entry and return
mechanisms automatically update the CONTROL register based on the EXC_RETURN value,
see Table 2-17 on page 2-28.
BASEPRIReserved
31 078
Table 2-9 BASEPRI register bit assignments
Bits Name Function
[31:8] - Reserved
[7:0]
BASEPRI
a
Priority mask bits:
0x00 = no effect
Nonzero = defines the base priority for exception processing.
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
a. This field is similar to the priority fields in the interrupt priority registers. Register priority value fields are eight bits wide, and
non-implemented low-order bits read as zero and ignore writes. See Interrupt Priority Registers on page 4-7 for more information.
Remember that higher priority field values correspond to lower exception priorities.
Table 2-10 CONTROL register bit assignments
Bits Name Function
[31:3] - Reserved.
[2] FPCA When floating-point is implemented this bit indicates whether context floating-point is currently active:
0 = no floating-point context active
1 = floating-point context active.
The Cortex-M4 uses this bit to determine whether to preserve floating-point state when processing an exception.
[1] SPSEL Defines the currently active stack pointer: In Handler mode this bit reads as zero and ignores writes. The
Cortex-M4 updates this bit automatically on exception return:
0 = MSP is the current stack pointer
1 = PSP is the current stack pointer.
[0] nPRIV Defines the Thread mode privilege level:
0 = privileged
1 = unprivileged.