ARM Cortex-M4 - LDR and STR, Immediate Offset

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-24
ID121610 Non-Confidential
3.4.2 LDR and STR, immediate offset
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed
immediate offset.
Syntax
op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
op{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
op{type}{cond} Rt, [Rn], #offset ; post-indexed
opD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, two words
opD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, two words
opD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, two words
where:
op Is one of:
LDR Load Register.
STR Store Register.
type Is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits ( LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits ( LDR only).
- omit, for word.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rt Specifies the register to load or store.
Rn Specifies the register on which the memory address is based.
offset Specifies an offset from Rn . If offset is omitted, the address is the contents of Rn .
Rt2 Specifies the additional register to load or store for two-word operations.