Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-19
ID121610 Non-Confidential
4.3.6 System Control Register
The SCR controls features of entry to and exit from low power state. See the register summary
in Table 4-12 on page 4-11 for its attributes. The bit assignments are:
4.3.7 Configuration and Control Register
The CCR controls entry to Thread mode and enables:
• the handlers for NMI, hard fault and faults escalated by FAULTMASK to ignore
BusFaults
• trapping of divide by zero and unaligned accesses
• access to the STIR by unprivileged software, see Software Trigger Interrupt Register on
page 4-8.
See the register summary in Table 4-12 on page 4-11 for the CCR attributes.
31 4 3 2 1 0
Reserved
Reserved
SLEEPDEEP
SLEEPONEXIT
Reserved
5
SEVONPEND
Table 4-19 SCR bit assignments
Bits Name Function
[31:5] - Reserved.
[4] SEVONPEND Send Event on Pending bit:
0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are
excluded
1 = enabled events and all interrupts, including disabled interrupts, can wakeup the
processor.
When an event or interrupt enters pending state, the event signal wakes up the processor
from WFE. If the processor is not waiting for an event, the event is registered and affects the
next WFE.
The processor also wakes up on execution of an
SEV
instruction or an external event.
[3] - Reserved.
[2] SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = sleep
1 = deep sleep.
[1] SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode:
0 = do not sleep when returning to Thread mode.
1 = enter sleep, or deep sleep, on return from an ISR.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty
main application.
[0] - Reserved.
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