ARM Cortex-M4 - Vcmp, Vcmpe

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-130
ID121610 Non-Confidential
3.11.3 VCMP, VCMPE
Compares two floating-point registers, or one floating-point register and zero.
Syntax
VCMP{E}{cond}.F32 Sd, Sm
VCMP{E}{cond}.F32 Sd, #0.0
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
E If present, any NaN operand causes an Invalid Operation exception. Otherwise,
only a signaling
NaN causes the exception.
Sd Specifies the floating-point operand to compare.
Sm Specifies the floating-point operand that is compared with.
Operation
This instruction:
1. Compares:
• Two floating-point registers.
• One floating-point register and zero.
2. Writes the result to the
FPSCR flags.
Restrictions
This instruction can optionally raise an
Invalid Operation exception if either operand is any type
of
NaN . It always raises an Invalid Operation exception if either operand is a signaling NaN .
Condition flags
When this instruction writes the result to the
FPSCR flags, the values are normally transferred to
the ARM flags by a subsequent
VMRS instruction, see VMRS on page 3-146.
Examples
VCMP.F32 S4, #0.0VCMP.F32 S4, S2