The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-29
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2.4 Fault handling
Faults are a subset of the exceptions, see Exception model on page 2-21. Faults are generated by:
• a bus error on:
— an instruction fetch or vector table load
— a data access.
• an internally-detected error such as an undefined instruction
• attempting to execute an instruction from a memory region marked as Execute-never
(XN).
• If your device contains an MPU, a privilege violation or an attempt to access an
unmanaged region causing an MPU fault.
2.4.1 Fault types
Table 2-18 shows the types of fault, the handler used for the fault, the corresponding fault status
register, and the register bit that indicates that the fault has occurred. See Configurable Fault
Status Register on page 4-24 for more information about the fault status registers.
Table 2-18 Faults
Fault Handler Bit name Fault status register
Bus error on a vector read HardFault VECTTBL HardFault Status Register on
page 4-30
Fault escalated to a hard fault FORCED
MPU or default memory map mismatch: MemManage - -
on instruction access
IACCVIOL
a
MemManage Fault Address
Register on page 4-30
on data access DACCVIOL
during exception stacking MSTKERR
during exception unstacking MUNSKERR
during lazy floating-point state preservation MLSPERR
Bus error: BusFault - -
during exception stacking STKERR BusFault Status Register on
page 4-26
during exception unstacking UNSTKERR
during instruction prefetch IBUSERR
during lazy floating-point state preservation LSPERR
Precise data bus error PRECISERR
Imprecise data bus error IMPRECISERR
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