The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-6
ID121610 Non-Confidential
Interrupt Program Status Register
The IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
See the register summary in Table 2-2 on page 2-3 for its attributes. The bit assignments are:
Execution Program Status Register
The EPSR contains the Thumb state bit, and the execution state bits for either the:
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store
multiple instruction.
See the register summary in Table 2-2 on page 2-3 for the EPSR attributes. The bit assignments
are:
Table 2-5 IPSR bit assignments
Bits Name Function
[31:9] - Reserved
[8:0] ISR_NUMBER This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = HardFault
4 = MemManage
5 = BusFault
6 = UsageFault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0.
.
.
.
n+15 = IRQ(n-1)
a
see Exception types on page 2-21 for more information.
a. The number of interrupts, n, is implementation-defined, in the range 1-240.
Table 2-6 EPSR bit assignments
Bits Name Function
[31:27] - Reserved.
[26:25], [15:10] ICI Interruptible-continuable instruction bits, see Interruptible-continuable instructions
on page 2-7.
[26:25], [15:10] IT Indicates the execution state bits of the
IT
instruction, see IT on page 3-122.
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