ARM Cortex-M4 - About the Cortex-M4 Processor and Core Peripherals; Cortex-M4 Implementation

Introduction
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 1-2
ID121610 Non-Confidential
1.1 About the Cortex-M4 processor and core peripherals
The Cortex-M4 processor is a high performance 32-bit processor designed for the
microcontroller market. It offers significant benefits to developers, including:
• outstanding processing performance combined with fast interrupt handling
• enhanced system debug with extensive breakpoint and trace capabilities
• efficient processor core, system and memories
• ultra-low power consumption with integrated sleep mode and an optional deep sleep
mode
• platform security robustness, with optional integrated Memory Protection Unit (MPU).
Figure 1-1 Cortex-M4 implementation
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline
Harvard architecture, making it ideal for demanding embedded applications. The processor
delivers exceptional power efficiency through an efficient instruction set and extensively
optimized design, providing high-end processing hardware including optional
IEEE754-compliant single-precision floating-point computation, a range of single-cycle and
SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and
dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex-M4 processor implements
tightly-coupled system components that reduce processor area while significantly improving
interrupt handling and system debug capabilities. The Cortex-M4 processor implements a
version of the Thumb
®
instruction set based on Thumb-2 technology, ensuring high code density
and reduced program memory requirements. The Cortex-M4 instruction set provides the
exceptional performance expected of a modern 32-bit architecture, with the high code density
of 8-bit and 16-bit microcontrollers.
The Cortex-M4 processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a
Non Maskable Interrupt (NMI) that can provide up to 256 interrupt priority levels. The tight
integration of the processor core and NVIC provides fast execution of Interrupt Service
Optional
Embedded
Trace Macrocell
NVIC
Optional
Debug
Access Port
Optional Memory
protection unit
Optional
WIC
Optional
Serial Wire
viewer
Bus matrix
Code
interface
SRAM and
peripheral interface
Optional
Data
watchpoints
Optional
Flash
patch
Cortex-M4
processor
Optional FPU
Processor
core