ARM Cortex-M4 - PKHBT and PKHTB

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-108
ID121610 Non-Confidential
3.8.1 PKHBT and PKHTB
Pack Halfword.
Syntax
op{cond} {Rd}, Rn, Rm {, LSL #imm}
op{cond} {Rd}, Rn, Rm {, ASR #imm}
where:
op Is one of:
PKHBT Pack Halfword, bottom and top with shift.
PKHTB Pack Halfword, top and bottom with shift.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register.
Rn Specifies the first operand register.
Rm Specifies the second operand register holding the value to be optionally shifted.
imm Specifies the shift length. The type of shift length depends on the instruction:
For
PKHBT :
LSL A left shift with a shift length from 1 to 31, 0 means no shift.
For
PKHTB :
ASR An arithmetic shift right with a shift length from 1 to 32, a shift of
32-bits is encoded as
0b00000 .
Operation
The PKHBT instruction:
1. Writes the value of the bottom halfword of the first operand to the bottom halfword of the
destination register.
2. If shifted, the shifted value of the second operand is written to the top halfword of the
destination register.
The
PKHTB instruction:
1. Writes the value of the top halfword of the first operand to the top halfword of the
destination register.
2. If shifted, the shifted value of the second operand is written to the bottom halfword of the
destination register.
Restrictions
Rd must not be SP and must not be PC.
Condition flags
This instruction does not change the flags.