Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-42
ID121610 Non-Confidential
The bit assignments are:
For information about access permission, see MPU access permission attributes on page 4-43.
SIZE field values
The SIZE field defines the size of the MPU memory region specified by the RNR. as follows:
(Region size in bytes) = 2
(SIZE+1)
XN
Reserved
31 29 28 27 26 24 23 22 21 19 18 17 16 15 8 7 6 5 1 0
AP TEX S C B SRD SIZE
ENABLE
Reserved
Reserved
Reserved
Table 4-43 MPU_RASR bit assignments
Bits Name Function
[31:29] - Reserved.
[28] XN Instruction access disable bit:
0 = instruction fetches enabled
1 = instruction fetches disabled.
[27] - Reserved.
[26:24] AP Access permission field, see Table 4-47 on page 4-44.
[23:22] - Reserved.
[21:19, 17, 16] TEX, C, B Memory access attributes, see Table 4-45 on page 4-43.
[18] S Shareable bit, see Table 4-45 on page 4-43.
[15:8] SRD Subregion disable bits. For each bit in this field:
0 = corresponding sub-region is enabled
1 = corresponding sub-region is disabled
See Subregions on page 4-46 for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes
for such a region, write the SRD field as
0x00
.
[7:6] - Reserved.
[5:1] SIZE Specifies the size of the MPU protection region. The minimum permitted value is 3
(
0b00010
). See SIZE field values for more information.
[0] ENABLE Region enable bit.
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