ARM Cortex-M4 - Conditional Execution

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-18
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3.3.7 Conditional execution
Most data processing instructions can optionally update the condition flags in the Application
Program Status Register (APSR) according to the result of the operation, see Application
Program Status Register on page 2-5. Some instructions update all flags, and some only update
a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions
for the flags they affect.
You can execute an instruction conditionally, based on the condition flags set in another
instruction, either:
• immediately after the instruction that updated the flags
• after any number of intervening instructions that have not updated the flags.
Conditional execution is available by using conditional branches or by adding condition code
suffixes to instructions. See Table 3-4 on page 3-19 for a list of the suffixes to add to instructions
to make them conditional instructions. The condition code suffix enables the processor to test a
condition based on the flags. If the condition test of a conditional instruction fails, the
instruction:
• does not execute
• does not write any value to its destination register
• does not affect any of the flags
• does not generate any exception.
Conditional instructions, except for conditional branches, must be inside an If-Then instruction
block. See IT on page 3-122 for more information and restrictions when using the
IT instruction.
Depending on the vendor, the assembler might automatically insert an
IT instruction if you have
conditional instructions outside the IT block.
Use the
CBZ and CBNZ instructions to compare the value of a register against zero and branch on
the result.
This section describes:
• The condition flags on page 3-19
• Condition code suffixes on page 3-19.