ARM Cortex-M4 - Isb; Instruction Synchronization Barrier

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-162
ID121610 Non-Confidential
3.12.5 ISB
Instruction Synchronization Barrier.
Syntax
ISB{cond}
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that
all instructions following the
ISB are fetched from cache or memory again, after the ISB
instruction has been completed.
Condition flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier