ARM Cortex-M4 - AP Encoding; MPU Mismatch; Updating an MPU Region; Updating an MPU Region Using Separate Words

Cortex-M4 Peripherals
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Table 4-46 shows the cache policy for memory attribute encodings with a TEX value is in the
range 4-7.
Table 4-47 shows the AP encodings that define the access permissions for privileged and
unprivileged software.
4.5.7 MPU mismatch
When an access violates the MPU permissions, the processor generates a MemManage fault, see
Exceptions and interrupts on page 2-10. The MMFSR indicates the cause of the fault. See
MemManage Fault Status Register on page 4-25 for more information.
4.5.8 Updating an MPU region
To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and
MPU_RASR registers. You can program each register separately, or use a multiple-word write
to program all of these registers. You can use the MPU_RBAR and MPU_RASR aliases to
program up to four regions simultaneously using an
STM instruction.
Updating an MPU region using separate words
Simple code to configure one region:
; R1 = region number
; R2 = size/enable
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
Table 4-46 Cache policy for memory attribute encoding
Encoding, AA or BB Corresponding cache policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate
Table 4-47 AP encoding
AP[2:0]
Privileged
permissions
Unprivileged
permissions
Description
000 No access No access All accesses generate a permission fault
001 RW No access Access from privileged software only
010 RW RO Writes by unprivileged software generate a permission fault
011 RW RW Full access
100 Unpredictable Unpredictable Reserved
101 RO No access Reads by privileged software only
110 RO RO Read only, by privileged or unprivileged software
111 RO RO Read only, by privileged or unprivileged software