ARM Cortex-M4 - VMOV ARM Core Register to Scalar

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-145
ID121610 Non-Confidential
3.11.18 VMOV ARM Core register to scalar
Transfers one word to a floating-point register from an ARM core register.
Syntax
VMOV{cond}{.32} Dd[x], Rt
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
32 Is an optional data size specifier.
Dd[x] Specifies the destination, where [x] defines which half of the doubleword is
transferred, as follows:
•If x is 0, the lower half is extracted
•If x is 1, the upper half is extracted.
Rt Specifies the source ARM core register.
Operation
This instruction transfers one word to the upper or lower half of a doubleword floating-point
register from an ARM core register.
Restrictions
Rt cannot be PC or SP.
Condition flags
These instructions do not change the flags.