ARM Cortex-M4 - Software Ordering of Memory Accesses; Instruction Prefetch and Branch Prediction; MPU Programming

The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-15
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Instruction prefetch and branch prediction
The Cortex-M4 processor:
• prefetches instructions ahead of execution
• speculatively prefetches from branch target addresses.
2.2.4 Software ordering of memory accesses
The order of instructions in the program flow does not always guarantee the order of the
corresponding memory transactions. This is because:
• the processor can reorder some memory accesses to improve efficiency, providing this
does not affect the behavior of the instruction sequence.
• the processor has multiple bus interfaces
• memory or devices in the memory map have different wait states
• some memory accesses are buffered or speculative.
Memory system ordering of memory accesses on page 2-13 describes the cases where the
memory system guarantees the order of memory accesses. Otherwise, if the order of memory
accesses is critical, software must include memory barrier instructions to force that ordering.
The processor provides the following memory barrier instructions:
DMB The Data Memory Barrier (DMB) instruction ensures that outstanding
memory transactions complete before subsequent memory transactions.
See DMB on page 3-160.
DSB The Data Synchronization Barrier (DSB) instruction ensures that
outstanding memory transactions complete before subsequent instructions
execute. See DSB on page 3-161.
ISB The Instruction Synchronization Barrier (ISB) ensures that the effect of all
completed memory transactions is recognizable by subsequent
instructions. See ISB on page 3-162.
MPU programming
Use a
DSB followed by an ISB instruction or exception return to ensure that the new MPU
configuration is used by subsequent instructions.
0xA0000000 - 0xBFFFFFFF External device
Device
a
Shareable
a
-
0xC0000000 - 0xDFFFFFFF
Non-shareable
a
0xE0000000 - 0xE00FFFFF Private Peripheral Bus
Strongly- ordered
a
Shareable
a
-
0xE0100000 - 0xFFFFFFFF Device Device - -
a. See Memory regions, types and attributes on page 2-12 for more information.
b. WT = Write through, no write allocate. WBWA = Write back, write allocate. See the Glossary for more information.
Table 2-12 Memory region shareability and cache policies (continued)
Address range Memory region Memory type Shareability Cache policy