The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-50
ID121610 Non-Confidential
3.5.6 MOV and MVN
Move and Move NOT.
Syntax
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2
where:
S
Is an optional suffix. If
S
is specified, the condition code flags are updated on the
result of the operation, see Conditional execution on page 3-18.
cond
Is an optional condition code. See Conditional execution on page 3-18.
Rd
Specifies the destination register.
Operand2
Is a flexible second operand, see Flexible second operand on page 3-12 for details
of the options.
imm16
Is any value in the range 0-65535.
Operation
The
MOV
instruction copies the value of
Operand2
into
Rd
.
When
Operand2
in a
MOV
instruction is a register with a shift other than
LSL #0
, the preferred
syntax is the corresponding shift instruction:
•
ASR{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, ASR #n
•
LSL{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, LSL #n
if
n
!= 0
•
LSR{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, LSR #n
•
ROR{S}{cond} Rd, Rm, #n
is the preferred syntax for
MOV{S}{cond} Rd, Rm, ROR #n
•
RRX{S}{cond} Rd, Rm
is the preferred syntax for
MOV{S}{cond} Rd, Rm, RRX
.
Also, the
MOV
instruction permits additional forms of
Operand2
as synonyms for shift instructions:
•
MOV{S}{cond} Rd, Rm, ASR Rs
is a synonym for
ASR{S}{cond} Rd, Rm, Rs
•
MOV{S}{cond} Rd, Rm, LSL Rs
is a synonym for
LSL{S}{cond} Rd, Rm, Rs
•
MOV{S}{cond} Rd, Rm, LSR Rs
is a synonym for
LSR{S}{cond} Rd, Rm, Rs
•
MOV{S}{cond} Rd, Rm, ROR Rs
is a synonym for
ROR{S}{cond} Rd, Rm, Rs
See ASR, LSL, LSR, ROR, and RRX on page 3-46.
The
MVN
instruction takes the value of
Operand2
, performs a bitwise logical NOT operation on the
value, and places the result into
Rd
.
The
MOVW
instruction provides the same function as
MOV
, but is restricted to using the
imm16
operand.
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