The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-51
ID121610 Non-Confidential
Restrictions
You can use SP and PC only in the
MOV
instruction, with the following restrictions:
• the second operand must be a register without shift
• you must not specify the S suffix.
When
Rd
is PC in a
MOV
instruction:
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
Though it is possible to use
MOV
as a branch instruction, ARM strongly recommends the use of
a
BX
or
BLX
instruction to branch for software portability to the ARM instruction set.
Condition flags
If
S
is specified, these instructions:
• update the N and Z flags according to the result
• can update the C flag during the calculation of
Operand2
, see Flexible second operand on
page 3-12
• do not affect the V flag.
Example
MOVS R11, #0x000B ; Write value of 0x000B to R11, flags get updated
MOV R1, #0xFA05 ; Write value of 0xFA05 to R1, flags are not updated
MOVS R10, R12 ; Write value in R12 to R10, flags get updated
MOV R3, #23 ; Write value of 23 to R3
MOV R8, SP ; Write value of stack pointer to R8
MVNS R2, #0xF ; Write value of 0xFFFFFFF0 (bitwise inverse of 0xF)
; to the R2 and update flags.
To Next Page
Loading...
