ARM Cortex-M4 - System Handler Priority Register 2; System Handler Priority Register 3

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-22
ID121610 Non-Confidential
System Handler Priority Register 2
The bit assignments are:
System Handler Priority Register 3
The bit assignments are:
Table 4-22 SHPR2 register bit assignments
Bits Name Function
[31:24] PRI_11 Priority of system handler 11, SVCall
[23:0] - Reserved.
Table 4-23 SHPR3 register bit assignments
Bits Name Function
[31:24] PRI_15 Priority of system handler 15, SysTick exception
[23:16] PRI_14 Priority of system handler 14, PendSV
[15:0] - Reserved.
31 24 23 0
PRI_11 Reserved
PRI_15
31 15 01624 23
PRI_14 Reserved