ARM Cortex-M4 - Cortex-M4 Implementation Options; A-1 Effects of the Cortex-M4 Implementation Options; Floating-Point Instructions on Page

Cortex-M4 Options
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A.1 Cortex-M4 implementation options
Table A-1 shows the Cortex-M4 implementation options:
Table A-1 Effects of the Cortex-M4 implementation options
Option Description, and affected documentation
Inclusion of
MPU
The implementer decides whether to include the Memory Protection Unit (MPU). See the Optional
Memory Protection Unit on page 4-37.
Inclusion of FPU Only the Cortex-M4F includes the Floating Point Unit (FPU). See:
• Floating-point instructions on page 3-126
• Interruptible-continuable instructions in Core registers on page 2-3
• The FPACTV bit in the CONTROL register
• Table 2-17 on page 2-28
• the MLSPERR bit in the MemManage Fault Status Register (MMFSR)
• the LSPERR bit in the BusFault Status Register (BFSR).
Number of
interrupts
The implementer decides how many interrupts the Cortex-M4 implementation supports Cortex-M4
implementation supports, in the range 1-240. This affects:
The range of IRQ values in Table 2-5 on page 2-6
Entries in the last row of Table 2-16 on page 2-22, particularly if only one interrupt is implemented.
The maximum interrupt number, and associated information where appropriate, in:
• Exception handlers on page 2-23
• Figure 2-2 on page 2-24
• Nested Vectored Interrupt Controller on page 4-3.
The number of implemented Nested Vectored Interrupt Controller (NVIC) registers in:
• Table 4-2 on page 4-3
• The appropriate register descriptions in sections Interrupt Set-enable Registers on page 4-4
to Interrupt Priority Registers on page 4-7.
Vector Table Offset Register on page 4-16, including the figure and Table 4-16 on page 4-16. See the
configuration information in the section for guidance on the required configuration.
Number of
priority bits
The implementer decides how many priority bits are implemented in priority value fields, in the range
3-8. This affects The maximum priority level value in Nested Vectored Interrupt Controller on
page 4-3.
Inclusion of the
WIC
The implementer decides whether to include the Wakeup interrupt Controller (WIC), see The optional
Wakeup Interrupt Controller on page 2-33.
Sleep mode
power-saving
The implementer decides what sleep modes to implement, and the power-saving measures associated
with any implemented mode, See Power management on page 2-32
.
Sleep mode power saving might also affect the SysTick behavior, see SysTick usage hints and tips on
page 4-36.
Register reset
values
The implementer decides whether all registers in the register bank can be reset. This affects the reset
values, see Table 2-2 on page 2-3.
Endianness The implementer decides whether the memory system is little-endian or big-endian, see on
page 2-10Data types on page 2-10 and Memory endianness on page 2-18.
Memory features Some features of the memory system are implementation-specific. This means that the Memory model
on page 2-12 cannot completely describe the memory map for a specific Cortex-M4 implementation.