ARM Cortex-M4 - SMLSD and SMLSLD

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-84
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3.6.6 SMLSD and SMLSLD
Signed Multiply Subtract Dual and Signed Multiply Subtract Long Dual.
Syntax
op{X}{cond} Rd, Rn, Rm, Ra
where:
op Is one of:
SMLSD Signed Multiply Subtract Dual.
SMLSDX Signed Multiply Subtract Dual Reversed.
SMLSLD Signed Multiply Subtract Long Dual.
SMLSLDX Signed Multiply Subtract Long Dual Reversed.
If
X is present, the multiplications are bottom × top and top × bottom. If the X is
omitted, the multiplications are bottom × bottom and top × top.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register.
Rn, Rm Are registers holding the first and second operands.
Ra Specifies the register holding the accumulate value.
Operation
The
SMLSD instruction interprets the values from the first and second operands as four signed
halfwords. This instruction:
• Optionally rotates the halfwords of the second operand.
• Performs two signed 16 × 16-bit halfword multiplications.
• Subtracts the result of the upper halfword multiplication from the result of the lower
halfword multiplication.
• Adds the signed accumulate value to the result of the subtraction.
• Writes the result of the addition to the destination register.
The
SMLSLD instruction interprets the values from Rn and Rm as four signed halfwords. This
instruction:
• Optionally rotates the halfwords of the second operand.
• Performs two signed 16 × 16-bit halfword multiplications.
• Subtracts the result of the upper halfword multiplication from the result of the lower
halfword multiplication.
• Adds the 64-bit value in
RdHi and RdLo to the result of the subtraction.
• Writes the 64-bit result of the addition to the
RdHi and RdLo .
Restrictions
In these instructions:
• Do not use SP and do not use PC.