ARM Cortex-M4 - Vldr; Loads a Single Extension Register from Memory

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-138
ID121610 Non-Confidential
3.11.11 VLDR
Loads a single extension register from memory.
Syntax
VLDR{cond}{.64} Dd, [Rn{#imm}]
VLDR{cond}{.64} Dd, label
VLDR{cond}{.64} Dd, [PC, #imm}]
VLDR{cond}{.32} Sd, [Rn {, #imm}]
VLDR{cond}{.32} Sd, label
VLDR{cond}{.32} Sd, [PC, #imm]
where:
cond Is an optional condition code, see Conditional execution on page 3-18.
64, 32 Are the optional data size specifiers.
Dd Specifies the destination register for a doubleword load.
Sd Specifies the destination register for a singleword load.
Rn Specifies the base register. The SP can be used.
imm Is the + or - immediate offset used to form the address. Permitted address values
are multiples of 4 in the range 0 to 1020.
label Specifies the label of the literal data item to be loaded.
Operation
This instruction:
• Loads a single extension register from memory, using a base address from an ARM core
register, with an optional offset.
Restrictions
There are no restrictions.
Condition flags
These instructions do not change the flags.