ARM Cortex-M4 - CPUID Base Register; Interrupt Control and State Register

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-13
ID121610 Non-Confidential
4.3.2 CPUID Base Register
The CPUID register contains the processor part number, version, and implementation
information. See the register summary in Table 4-12 on page 4-11 for its attributes. The bit
assignments are:
4.3.3 Interrupt Control and State Register
The ICSR:
• provides:
— a set-pending bit for the Non-Maskable Interrupt (NMI) exception
— set-pending and clear-pending bits for the PendSV and SysTick exceptions
• indicates:
— the exception number of the exception being processed
— whether there are preempted active exceptions
— the exception number of the highest priority pending exception
— whether any interrupts are pending.
Table 4-14 CPUID register bit assignments
Bits Name Function
[31:24] Implementer Implementer code:
0x41 = ARM
[23:20] Variant Variant number, the r value in the rnpn product revision identifier:
0x0 = Revision 0
[19:16] Constant Reads as
0xF
[15:4] PartNo Part number of the processor:
0xC24 = Cortex-M4
[3:0] Revision Revision number, the p value in the rnpn product revision identifier:
0x0 = Patch 0
31 16 15 4 3 0
Implementer
RevisionPartNo
24 23 20 19
Variant Constant