ARM Cortex-M4 - MPU Access Permission Attributes; Example SIZE Field Values; TEX, C, B, and S Encoding

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-43
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The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 4-44 gives
example SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
4.5.6 MPU access permission attributes
This section describes the MPU access permission attributes. The access permission bits, TEX,
C, B, S, AP, and XN, of the RASR, control access to the corresponding memory region. If an
access is made to an area of memory without the required permissions, then the MPU generates
a permission fault. Table 4-45 shows encodings for the TEX, C, B, and S access permission bits.
Table 4-44 Example SIZE field values
SIZE value Region size
Value of N
a
a. In the MPU_RBAR, see MPU Region Base Address Register on page 4-40.
Note
0b00100 (4) 32B 5 Minimum permitted size
0b01001 (9) 1KB 10 -
0b10011 (19) 1MB 20 -
0b11101 (29) 1GB 30 -
0b11111 (31) 4GB 32 Maximum possible size
Table 4-45 TEX, C, B, and S encoding
TEX C B S Memory type Shareability Other attributes
0b000 0 0
x
a
Strongly-ordered Shareable -
1
x
a
Device Shareable -
1 0 0 Normal Not shareable Outer and inner write-through. No write allocate.
1Shareable
1 0 Normal Not shareable Outer and inner write-back. No write allocate.
1Shareable
0b001 0 0 0 Normal Not shareable Outer and inner noncacheable.
1Shareable
1
x
a
Reserved encoding -
1 0
x
a
Implementation defined attributes. -
1 0 Normal Not shareable Outer and inner write-back. Write and read allocate.
1Shareable
0b010 00
x
a
Device Not shareable Nonshared Device.
1
x
a
Reserved encoding -
1
x
a
x
a
Reserved encoding -
0b1BB A A 0 Normal Not shareable Cached memory, BB = outer policy, AA = inner policy.
See Table 4-46 on page 4-44 for the encoding of the AA
and BB bits.
1Shareable
a. The MPU ignores the value of this bit.