ARM Cortex-M4 - MPU Control Register; MPU_CTRL Register Bit Assignments

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-39
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4.5.2 MPU Control Register
The MPU_CTRL register:
• enables the MPU
• enables the default memory map background region
• enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
See the register summary in Table 4-38 on page 4-38 for the MPU_CTRL attributes. The bit
assignments are:
When ENABLE and PRIVDEFENA are both set to 1:
• For privileged accesses, the default memory map is as described in Memory model on
page 2-12. Any access by privileged software that does not address an enabled memory
region behaves as defined by the default memory map.
• Any access by unprivileged software that does not address an enabled memory region
causes a MemManage fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the
value of the ENABLE bit.
31 10
Reserved
HFNMIENA
ENABLE
2
PRIVDEFENA
3
Table 4-40 MPU_CTRL register bit assignments
Bits Name Function
[31:3] - Reserved.
[2] PRIVDEFENA Enables privileged software access to the default memory map:
0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a
location not covered by any enabled region causes a fault.
1 = If the MPU is enabled, enables use of the default memory map as a background region for
privileged software accesses.
When enabled, the background region acts as if it is region number -1. Any region that is
defined and enabled has priority over this default map.
If the MPU is disabled, the processor ignores this bit.
[1] HFNMIENA Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0 = MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the
value of the ENABLE bit
1 = the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
[0] ENABLE Enables the MPU:
0 = MPU disabled
1 = MPU enabled.