ARM Cortex-M4 - ASR, LSL, LSR, ROR, and RRX

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-46
ID121610 Non-Confidential
3.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right
with Extend.
Syntax
op{S}{cond} Rd, Rm, Rs
op{S}{cond} Rd, Rm, #n
RRX{S}{cond} Rd, Rm
where:
op Is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S Is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see Conditional execution on page 3-18.
Rd Specifies the destination register.
Rm Specifies the register holding the value to be shifted.
Rs Specifies the register holding the shift length to apply to the value in Rm . Only the
least significant byte is used and can be in the range 0 to 255.
n Specifies the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 1 to 31.
Note
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0 .