ARM Cortex-M4 - Vstm; Floating-Point Store Multiple

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-154
ID121610 Non-Confidential
3.11.27 VSTM
Floating-point Store Multiple.
Syntax
VSTM{mode}{cond}{.size} Rn{!}, list
where:
mode Specifies the addressing mode:
•IA Increment After. The consecutive addresses start at the address specified
in
Rn . This is the default and can be omitted.
•DB Decrement Before. The consecutive addresses end just before the
address specified in
Rn .
cond Is an optional condition code, see Conditional execution on page 3-18.
size Is an optional data size specifier. If present, it must be equal to the size in bits, 32
or 64, of the registers in
list .
Rn Specifies the base register. The SP can be used.
! is the function that causes the instruction to write a modified value back to Rn .
Required if
mode == DB .
list Is a list of the extension registers to be stored, as a list of consecutively numbered
doubleword or singleword registers, separated by commas and surrounded by
brackets.
Operation
This instruction:
• Stores multiple extension registers to consecutive memory locations using a base address
from an ARM core register.
Restrictions
The restrictions are:
•
list must contain at least one register. If it contains doubleword registers it must not
contain more than 16 registers.
• Use of the PC as
Rn is deprecated.
Condition flags
These instructions do not change the flags.