ARM Cortex-M4 - SMLA and SMLAW

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-79
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3.6.3 SMLA and SMLAW
Signed Multiply Accumulate (halfwords).
Syntax
op{XY}{cond} Rd, Rn, Rm
op{Y}{cond} Rd, Rn, Rm, Ra
where:
op Is one of:
SMLA Signed Multiply Accumulate Long (halfwords)
X and Y specifies which half of the source registers Rn and Rm are used
as the first and second multiply operand.
If
X is B , then the bottom halfword, bits [15:0], of Rn is used. If X is T ,
then the top halfword, bits [31:16], of
Rn is used.
If
Y is B , then the bottom halfword, bits [15:0], of Rm is used. If Y is T ,
then the top halfword, bits [31:16], of
Rm is used.
SMLAW Signed Multiply Accumulate (word by halfword)
Y specifies which half of the source register Rm is used as the second
multiply operand.
If
Y is T , then the top halfword, bits [31:16] of Rm is used.
If
Y is B , then the bottom halfword, bits [15:0] of Rm is used.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register. If Rd is omitted, the destination register is Rn .
Rn, Rm Are registers holding the values to be multiplied.
Ra Is a register holding the value to be added or subtracted from.
Operation
The
SMALBB , SMLABT , SMLATB , SMLATT instructions:
• Multiplies the specified signed halfword, top or bottom, values from
Rn and Rm .
• Adds the value in
Ra to the resulting 32-bit product.
• Writes the result of the multiplication and addition in
Rd .
The non-specified halfwords of the source registers are ignored.
The
SMLAWB and SMLAWT instructions:
• Multiply the 32-bit signed values in
Rn with:
— The top signed halfword of
Rm , T instruction suffix.
— The bottom signed halfword of
Rm , B instruction suffix.
• Add the 32-bit signed value in
Ra to the top 32 bits of the 48-bit product
• Writes the result of the multiplication and addition in
Rd .
The bottom 16 bits of the 48-bit product are ignored.
If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in
the APSR. No overflow can occur during the multiplication.