ARM Cortex-M4 - LDR and STR, Register Offset

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-27
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3.4.3 LDR and STR, register offset
Load and Store with register offset.
Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op Is one of:
LDR Load Register.
STR Store Register.
type Is one of:
B unsigned byte, zero extend to 32 bits on loads.
SB signed byte, sign extend to 32 bits ( LDR only).
H unsigned halfword, zero extend to 32 bits on loads.
SH signed halfword, sign extend to 32 bits ( LDR only).
- omit, for word.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rt Specifies the register to load or store.
Rn Specifies the register on which the memory address is based.
Rm Specifies the register containing a value to be used as the offset.
LSL #n Is an optional shift, with n in the range 0 to 3.
Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register
Rn . The offset is
specified by the register
Rm and can be shifted left by up to 3 bits using LSL .
The value to load or store can be a byte, halfword, or word. For load instructions, bytes and
halfwords can either be signed or unsigned. See Address alignment on page 3-17.
Restrictions
In these instructions:
•
Rn must not be PC
•
Rm must not be SP and must not be PC
•
Rt can be SP only for word loads and word stores
•
Rt can be PC only for word loads.
When
Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this
halfword-aligned address
• if the instruction is conditional, it must be the last instruction in the IT block.