ARM Cortex-M4 - Page 73

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-26
ID121610 Non-Confidential
Restrictions
For load instructions:
•
Rt can be SP or PC for word loads only
•
Rt must be different from Rt2 for two-word loads
•
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
When
Rt is PC in a word load instruction:
• bit[0] of the loaded value must be 1 for correct execution
• a branch occurs to the address created by changing bit[0] of the loaded value to 0
• if the instruction is conditional, it must be the last instruction in the IT block.
For store instructions:
•
Rt can be SP for word stores only
•
Rt must not be PC
•
Rn must not be PC
•
Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.
Condition flags
These instructions do not change the flags.
Examples
LDR R8, [R10] ; Loads R8 from the address in R10.
LDRNE R2, [R5, #960]! ; Loads (conditionally) R2 from a word
; 960 bytes above the address in R5, and
; increments R5 by 960
STR R2, [R9,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-4095.
STRH R3, [R4], #4 ; Store R3 as halfword data into address in
; R4, then increment R4 by 4
LDRD R8, R9, [R3, #0x20] ; Load R8 from a word 32 bytes above the
; address in R3, and load R9 from a word 36
; bytes above the address in R3
STRD R0, R1, [R8], #-16 ; Store R0 to address in R8, and store R1 to
; a word 4 bytes above the address in R8,
; and then decrement R8 by 16.