ARM Cortex-M4 - System Control Block

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-11
ID121610 Non-Confidential
4.3 System control block
The System Control Block (SCB) provides system implementation information, and system
control. This includes configuration, control, and reporting of the system exceptions. The
system control block registers are:
4.3.1 Auxiliary Control Register
The ACTLR provides disable bits for the following processor functions:
• IT folding
• write buffer use for accesses to the default memory map
• interruption of multi-cycle instructions.
By default this register is set to provide optimum performance from the Cortex-M4 processor,
and does not normally require modification.
Table 4-12 Summary of the system control block registers
Address Name Type
Required
privilege
Reset value Description
0xE000E008 ACTLR RW Privileged 0x00000000 Auxiliary Control Register
0xE000ED00 CPUID RO Privileged 0x410FC240 CPUID Base Register on page 4-13
0xE000ED04 ICSR
RW
a
Privileged 0x00000000 Interrupt Control and State Register on page 4-13
0xE000ED08 VTOR RW Privileged 0x00000000 Vector Table Offset Register on page 4-16
0xE000ED0C AIRCR
RW
a
Privileged 0xFA050000 Application Interrupt and Reset Control Register on page 4-16
0xE000ED10 SCR RW Privileged 0x00000000 System Control Register on page 4-19
0xE000ED14 CCR RW Privileged 0x00000200 Configuration and Control Register on page 4-19
0xE000ED18 SHPR1 RW Privileged 0x00000000 System Handler Priority Register 1 on page 4-21
0xE000ED1C SHPR2 RW Privileged 0x00000000 System Handler Priority Register 2 on page 4-22
0xE000ED20 SHPR3 RW Privileged 0x00000000 System Handler Priority Register 3 on page 4-22
0xE000ED24 SHCRS RW Privileged 0x00000000 System Handler Control and State Register on page 4-23
0xE000ED28 CFSR RW Privileged 0x00000000 Configurable Fault Status Register on page 4-24
0xE000ED28
MMSR
b
RW Privileged 0x00 MemManage Fault Status Register on page 4-25
0xE000ED29
BFSR
b
RW Privileged 0x00 BusFault Status Register on page 4-26
0xE000ED2A
UFSR
b
RW Privileged 0x0000 UsageFault Status Register on page 4-28
0xE000ED2C HFSR RW Privileged 0x00000000 HardFault Status Register on page 4-30
0xE000ED34 MMAR RW Privileged Unknown MemManage Fault Address Register on page 4-30
0xE000ED38 BFAR RW Privileged Unknown BusFault Address Register on page 4-31
0xE000ED3C AFSR RW Privileged 0x00000000 Auxiliary Fault Status Register on page 4-31
a. See the register description for more information.
b. A subregister of the CFSR.