ARM Cortex-M4 - Core Registers; Core Register Set Summary

The Cortex-M4 Processor
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 2-3
ID121610 Non-Confidential
2.1.3 Core registers
The processor core registers are:
SP (R13)
LR (R14)
PC (R15)
R5
R6
R7
R0
R1
R3
R4
R2
R10
R11
R12
R8
R9
Low registers
High registers
MSP
‡
PSP
‡
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
Stack Pointer
Link Register
Program Counter
Program status register
Exception mask registers
CONTROL register
Special registers
‡
Banked version of SP
Table 2-2 Core register set summary
Name
Type
a
Required privilege
b
Reset value Description
R0-R12 RW Either Unknown General-purpose registers on page 2-4
MSP RW Privileged See description Stack Pointer on page 2-4
PSP RW Either Unknown Stack Pointer on page 2-4
LR RW Either
0xFFFFFFFF Link Register on page 2-4
PC RW Either See description Program Counter on page 2-4
PSR RW Privileged
0x01000000 Program Status Register on page 2-4
ASPR RW Either Unknown Application Program Status Register on page 2-5
IPSR RO Privileged
0x00000000 Interrupt Program Status Register on page 2-6
EPSR RO Privileged
0x01000000 Execution Program Status Register on page 2-6
PRIMASK RW Privileged
0x00000000 Priority Mask Register on page 2-8
FAULTMASK RW Privileged
0x00000000 Fault Mask Register on page 2-8
BASEPRI RW Privileged
0x00000000 Base Priority Mask Register on page 2-9
CONTROL RW Privileged
0x00000000 CONTROL register on page 2-9
a. Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
b. An entry of Either means privileged and unprivileged software can access the register.