The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-22
ID121610 Non-Confidential
3.4 Memory access instructions
Table 3-5 shows the memory access instructions:
Table 3-5 Memory access instructions
Mnemonic Brief description See
ADR
Generate PC-relative address ADR on page 3-23
CLREX
Clear Exclusive CLREX on page 3-38
LDM{mode}
Load Multiple registers LDM and STM on page 3-32
LDR{type}
Load Register using immediate offset LDR and STR, immediate offset on page 3-24
LDR{type}
Load Register using register offset LDR and STR, register offset on page 3-27
LDR{type}T
Load Register with unprivileged access LDR and STR, unprivileged on page 3-29
LDR
Load Register using PC-relative address LDR, PC-relative on page 3-30
LDREX{type}
Load Register Exclusive LDREX and STREX on page 3-36
POP
Pop registers from stack PUSH and POP on page 3-34
PUSH
Push registers onto stack PUSH and POP on page 3-34
STM{mode}
Store Multiple registers LDM and STM on page 3-32
STR{type}
Store Register using immediate offset LDR and STR, immediate offset on page 3-24
STR{type}
Store Register using register offset LDR and STR, register offset on page 3-27
STR{type}T
Store Register with unprivileged access LDR and STR, unprivileged on page 3-29
STREX{type}
Store Register Exclusive LDREX and STREX on page 3-36
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