ARM Cortex-M4 - MPU Region Number Register; MPU Region Base Address Register; MPU

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Cortex-M4 Peripherals

ID121610 Non-Confidential

When the ENABLE bit is set to 1, at least one region of the memory map must be enabled for

the system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is set

to 1 and no regions are enabled, then only privileged software can operate.

When the ENABLE bit is set to 0, the system uses the default memory map. This has the same

memory attributes as if the MPU is not implemented, see Table 2-11 on page 2-14. The default

memory map applies to accesses from both privileged and unprivileged software.

When the MPU is enabled, accesses to the System Control Space and vector table are always

permitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1.

Unless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing the

handler for an exception with priority –1 or –2. These priorities are only possible when handling

a hard fault or NMI exception, or when FAULTMASK is enabled. Setting the HFNMIENA bit

to 1 enables the MPU when operating with these two priorities.

4.5.3 MPU Region Number Register

The MPU_RNR selects which memory region is referenced by the MPU_RBAR and

MPU_RASR registers. See the register summary in Table 4-38 on page 4-38 for its attributes.

The bit assignments are:

Normally, you write the required region number to this register before accessing the

MPU_RBAR or MPU_RASR. However you can change the region number by writing to the

MPU RBAR with the VALID bit set to 1, see MPU Region Base Address Register. This write

updates the value of the REGION field.

4.5.4 MPU Region Base Address Register

The MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, and

can update the value of the MPU_RNR. See the register summary in Table 4-38 on page 4-38

for its attributes.

Reserved

31 8 7 0

REGION

Table 4-41 MPU_RNR bit assignments

Bits Name Function

[31:8] - Reserved.

[7:0] REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.

The MPU supports 8 memory regions, so the permitted values of this field are 0-7.

ARM Cortex-M4 - MPU Region Number Register; MPU Region Base Address Register; MPU_RNR Bit Assignments