ARM Cortex-M4 - MPU Registers Summary; MPU Type Register; TYPE Register Bit Assignments

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-38
ID121610 Non-Confidential
Use the MPU registers to define the MPU regions and their attributes. The MPU registers are:
4.5.1 MPU Type Register
The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it
supports. See the register summary in Table 4-38 for its attributes. The bit assignments are:
Table 4-38 MPU registers summary
Address Name Type
Required
privilege
Reset
value
Description
0xE000ED90 MPU_TYPE RO Privileged 0x00000800 MPU Type Register
0xE000ED94 MPU_CTRL RW Privileged 0x00000000 MPU Control Register on page 4-39
0xE000ED98 MPU_RNR RW Privileged 0x00000000 MPU Region Number Register on page 4-40
0xE000ED9C MPU_RBAR RW Privileged 0x00000000 MPU Region Base Address Register on page 4-40
0xE000EDA0 MPU_RASR RW Privileged 0x00000000 MPU Region Attribute and Size Register on page 4-41
0xE000EDA4 MPU_RBAR_A1 RW Privileged 0x00000000 Alias of RBAR, see MPU Region Base Address Register on
page 4-40
0xE000EDA8 MPU_RASR_A1 RW Privileged 0x00000000 Alias of RASR, see MPU Region Attribute and Size Register
on page 4-41
0xE000EDAC MPU_RBAR_A2 RW Privileged 0x00000000 Alias of RBAR, see MPU Region Base Address Register on
page 4-40
0xE000EDB0 MPU_RASR_A2 RW Privileged 0x00000000 Alias of RASR, see MPU Region Attribute and Size Register
on page 4-41
0xE000EDB4 MPU_RBAR_A3 RW Privileged 0x00000000 Alias of RBAR, see MPU Region Base Address Register on
page 4-40
0xE000EDB8 MPU_RASR_A3 RW Privileged 0x00000000 Alias of RASR, see MPU Region Attribute and Size Register
on page 4-41
Reserved
31 24 23 16 15 8 7 1 0
IREGION DREGION Reserved
SEPARATE
Table 4-39 TYPE register bit assignments
Bits Name Function
[31:24] - Reserved.
[23:16] IREGION Indicates the number of supported MPU instruction regions.
Always contains
0x00 . The MPU memory map is unified and is described by the DREGION field.
[15:8] DREGION Indicates the number of supported MPU data regions:
0x08 = Eight MPU regions.
[7:1] - Reserved.
[0] SEPARATE Indicates support for unified or separate instruction and date memory maps:
0 = unified.