ARM Cortex-M4 - Vldm; Floating-Point Load Multiple

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-137
ID121610 Non-Confidential
3.11.10 VLDM
Floating-point Load Multiple.
Syntax
VLDM{mode}{cond}{.size} Rn{!}, list
where:
mode Specifies the addressing mode:
• IAIncrement After. The consecutive addresses start at the address specified
in Rn.
• DB Decrement Before. The consecutive addresses end just before
the address specified in Rn.
cond Is an optional condition code, see Conditional execution on page 3-18.
size Is an optional data size specifier.
Rn Specifies the base register. The SP can be used.
! Is the command to the instruction to write a modified value back to Rn . This is
required if
mode == DB , and is optional if mode == IA .
list Specifies the list of extension registers to be loaded, as a list of consecutively
numbered doubleword or singleword registers, separated by commas and
surrounded by brackets.
Operation
This instruction loads:
• Multiple extension registers from consecutive memory locations using an address from an
ARM core register as the base address.
Restrictions
The restrictions are:
• If
size is present, it must be equal to the size in bits, 32 or 64 , of the registers in list .
• For the base address, the SP can be used. In the ARM instruction set, if
! is not specified
the
PC can be used.
•
list must contain at least one register. If it contains doubleword registers, it must not
contain more than 16 registers.
• If using the
Decrement Before addressing mode, the write back flag, ! , must be appended
to the base register specification.
Condition flags
These instructions do not change the flags.