Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-24
ID121610 Non-Confidential
If you disable a system handler and the corresponding fault occurs, the processor treats the fault
as a hard fault.
You can write to this register to change the pending or active status of system exceptions. An
OS kernel can write to the active bits to perform a context switch that changes the current
exception type.
• Software that changes the value of an active bit in this register without correct adjustment
to the stacked content can cause the processor to generate a fault exception. Ensure
software that writes to this register retains and subsequently restores the current active
status.
• After you have enabled the system handlers, if you have to change the value of a bit in this
register you must use a read-modify-write procedure to ensure that you change only the
required bit.
4.3.10 Configurable Fault Status Register
The CFSR indicates the cause of a MemManage fault, BusFault, or UsageFault. See the register
summary in Table 4-12 on page 4-11 for its attributes. The bit assignments are:
The following subsections describe the subregisters that make up the CFSR:
• MemManage Fault Status Register on page 4-25
• BusFault Status Register on page 4-26
• UsageFault Status Register on page 4-28.
The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
• access the complete CFSR with a word access to
0xE000ED28
• access the MMFSR with a byte access to
0xE000ED28
• access the MMFSR and BFSR with a halfword access to
0xE000ED28
• access the BFSR with a byte access to
0xE000ED29
• access the UFSR with a halfword access to
0xE000ED2A
.
[2] - Reserved.
[1] BUSFAULTACT BusFault exception active bit, reads as 1 if exception is active
[0] MEMFAULTACT MemManage exception active bit, reads as 1 if exception is active
a. Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
b. Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending
status of the exceptions.
c. Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status
of the exceptions, but see the Caution in this section.
Table 4-24 SHCSR bit assignments (continued)
Bits Name Function
Memory Management
Fault Status Register
31 16 15 8 7 0
Usage Fault Status Register
Bus Fault Status
Register
UFSR BFSR MMFSR
To Next Page
Loading...
