ARM Cortex-M4 - Floating-Point Default Status Control Register; FPDSCR Register Bit Assignments; Enabling the FPU

Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-52
ID121610 Non-Confidential
4.6.5 Floating-point Default Status Control Register
The FPDSCR register holds the default values for the floating-point status control data. See the
register summary in Cortex-M4F floating-point system registers on page 4-48 for its attributes.
The bit assignments are:
4.6.6 Enabling the FPU
The FPU is disabled from reset. You must enable it before you can use any floating-point
instructions. Example 4-1 shows an example code sequence for enabling the FPU in both
privileged and user modes. The processor must be in privileged mode to read from and write to
the CPACR.
Example 4-1 Enabling the FPU
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB
Table 4-54 FPDSCR register bit assignments
Bits Name Function
[31:27] - Reserved
[26] AHP Default value for FPSCR.AHP
[25] DN Default value for FPSCR.DN
[24] FZ Default value for FPSCR.FZ
[23:22] RMode Default value for FPSCR.RMode
[21:0] - Reserved
0Reserved
31 27 26 25 24 23 22 21 0
0 0 0 0 Reserved
AHP RMode
DN FZ