Cortex-M4 Peripherals
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 4-51
ID121610 Non-Confidential
[26] AHP Alternative half-precision control bit:
0 IEEE half-precision format selected.
1 Alternative half-precision format selected.
[25] DN Default NaN mode control bit:
0 NaN operands propagate through to the output of a floating-point operation.
1 Any operation involving one or more NaNs returns the Default NaN.
[24] FZ Flush-to-zero mode control bit:
0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully
compliant with the IEEE 754 standard.
1 Flush-to-zero mode enabled.
[23:22] RMode Rounding Mode control field. The encoding of this field is:
0b00 Round to Nearest (RN) mode
0b01 Round towards Plus Infinity (RP) mode
0b10 Round towards Minus Infinity (RM) mode
0b11 Round towards Zero (RZ) mode.
The specified rounding mode is used by almost all floating-point instructions.
[21:8] - Reserved.
[7] IDC Input Denormal cumulative exception bit, see bits [4:0].
[6:5] - Reserved.
[4] IXC Cumulative exception bits for floating-point exceptions, see also bit [7]. Each of these bits is
set to 1 to indicate that the corresponding exception has occurred since 0 was last written to it.
IDC, bit[7] Input Denormal cumulative exception bit.
IXC Inexact cumulative exception bit.
UFC Underflow cumulative exception bit.
OFC Overflow cumulative exception bit.
DZC Division by Zero cumulative exception bit.
IOC Invalid Operation cumulative exception bit.
[3] UFC
[2] OFC
[1] DZC
[0] IOC
Table 4-53 FPSCR bit assignments (continued)
Bits Name Function
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