ARM Cortex-M4 - ADD, ADC, SUB, SBC, and RSB

The Cortex-M4 Instruction Set
ARM DUI 0553A Copyright © 2010 ARM. All rights reserved. 3-41
ID121610 Non-Confidential
3.5.1 ADD, ADC, SUB, SBC, and RSB
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
Syntax
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only
where:
op Is one of:
ADD Add.
ADC Add with Carry.
SUB Subtract.
SBC Subtract with Carry.
RSB Reverse Subtract.
S Is an optional suffix. If S is specified, the condition code flags are updated on the
result of the operation, see Conditional execution on page 3-18.
cond Is an optional condition code, see Conditional execution on page 3-18.
Rd Specifies the destination register. If Rd is omitted, the destination register is Rn .
Rn Specifies the register holding the first operand.
Operand2 Is a flexible second operand. See Flexible second operand on page 3-12 for
details of the options.
imm12 Is any value in the range 0-4095.
Operation
The
ADD instruction adds the value of Operand2 or imm12 to the value in Rn .
The
ADC instruction adds the values in Rn and Operand2 , together with the carry flag.
The
SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn .
The
SBC instruction subtracts the value of Operand2 from the value in Rn . If the carry flag is clear,
the result is reduced by one.
The
RSB instruction subtracts the value in Rn from the value of Operand2 . This is useful because
of the wide range of options for
Operand2 .
Use
ADC and SBC to synthesize multiword arithmetic, see Multiword arithmetic examples on
page 3-42.
See also ADR on page 3-23.
Note
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the SUB
syntax that uses the
imm12 operand.